module top_count32 #(
    parameter base_clk = 50_000_000,
    parameter clk1 = 10,
    parameter clk2 = 1_000
) (
    input            CLK,
    input            EN,
    input            RST,
    output reg [7:0] SEG,
    output reg [7:0] WORD_SEL
);
  wire [24:0] get_clk10, get_clk1000;
  wire clk10, clk1000;
  wire [31:0] out_wire;
  assign get_clk10   = base_clk / (2 * clk1);
  assign get_clk1000 = base_clk / (2 * clk2);
  Freq_div freq_div_10 (
      .clk(CLK),
      .N  (get_clk10),
      .out(clk10)
  );
  Freq_div freq_div_1000 (
      .clk(CLK),
      .N  (get_clk1000),
      .out(clk1000)
  );
  counter count32 (
      .clk(clk10),
      .rst(RST),
      .en (EN),
      .cnt(out_wire)
  );
  disp_scan ds (
      .CLK     (clk1000),
      .DATA_in (out_wire[3:0]),
      .SEG     (SEG),
      .WORD_SEL(WORD_SEL)
  );
endmodule
